Many present day digital computers include bi-directional buses for transmitting data and control signals to and from various sub systems. Such systems often include integrated circuits connected to the bus which have bi-directional drivers/receivers, or tranceivers connected to the same signal pad or pin. In such systems the transceiver functionality is achieved by connecting the output drivers output circuit line and the input receivers input circuit line to the same I/O signal pad or pin.
For example, copending application Ser. No. 07/123,507 filed Nov. 20, 1987, and now U.S. Pat. No. 4,806,800 entitled "True TTL to True ECL Input Translator Driver Circuit" shows a receiver circuit, and copending application Ser. No. 07/123,093 filed Nov. 20, 1987 entitled "True and now U.S. Pat. No. 4,857,776 TTL Output Translator Driver with True ECL Tri-State Control" shows a driver circuit. The two circuits shown in these applications could be connected to the same I/O signal pad or pin.
Many integrated circuit chips are I-O bound, that is, the area of the chip is controlled by the number of I-O bonding pads required to get signals on and off the chip. In such chips, there generally is adequate space for the actual logic circuits. However, in some modern technology such as TAB technology, the I-O bonding pads are very closely spaced and there are substantially more I-O bonding pads available. In such circuits the area density of the I-O logic circuits becomes a critical factor. Stated differently, the smaller the area required for I-O units, the smaller the overall chip dimensions possible. Such chip dimensions are desirable because they result in higher yield and lower cost.
The present invention addresses the problem of I-O circuit cell density in a situation where a common bonding pad is used for a bi-directional driver/receiver. Conventional transceivers which have two distinct functional circuit blocks, that is, a separate receiver circuit and a separate driver circuit, are relatively high in both component count and in use of silicon chip real estate. High component count and high use of silicon chip real estate has negative implications with respect to parameters such as die size, chip cost, yield, chip logic functional capability, etc.